2/28/2024 0 Comments Nvidia keynote ces 2021![]() As we've previously reported, higher TDPs are already causing headaches for data center operators, especially those looking to deploy AI infrastructure at scale. "The more you can integrate, the less energy you're having to expend to go to - that drives quite a bit of energy… - but there's innovation coming," he said.Įven so, hotter chips still pose a challenge with regard to thermal management. Packing more compute into a single package is going to require more power, but it does help to reduce the amount needed to move data around. This approach doesn't change the fact Moore's Law is slowing down. Speaking of the MI300A - the "A" here standing for APU - AMD actually developed a technology called Smart Shift to dynamically divvy up power between the chip's 24 Zen 4 cores and its six CDNA 3 GPU dies depending on the workload. Available in an APU and GPU form factor the chip is assembled from as many as 13 smaller chiplets - not counting the eight high-bandwidth memory stacks - and meshing them together using high-performance silicon interconnects. This is exactly what AMD did with its MI300-series accelerators announced this week. ![]() This approach can be extended through the use of advanced packaging to increase the density of a single product beyond the reticle limit. This is the reason AMD's Epyc 4 CPUs use a 6nm process node for I/O and a 5nm node for the compute dies. The thinking is that certain elements scale better with process shrinks than others. One of the first ways AMD optimized power efficiency was by desegregating compute from I/O and memory and then using the best available process tech for each. "We're on such an exponential curve of both compute and higher energy consumption that what have to think about is what are the levers you have to bend the curve."įrom the beginning, AMD has emphasized a mix of general, accelerated, and domain specific compute capabilities, addressed largely by its portfolio of CPUs, GPUs, FPGAs, and accelerator IP.ĪMD has also invested heavily in a number of technologies including chiplets and advanced packaging to engineer around the limits of modern semiconductor manufacturing techniques. This is an incredibly complex problem to solve and there is no one big lever you can pull to solve it, Papermaster explains. With AMD's deadline fast approaching the chip biz has made significant progress, but it still has a long way to go, having achieved just 13.5x improvement so far.
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